As an integration of a memory device is increased, the memory device may have a multiple bank structure including a plurality of banks A pre-charge operation on the memory device including a plurality of banks may include a pre-charge operation of performing a pre-charge on each bank and/or an all bank pre-charge operation of performing the pre-charge on all banks at the same time. The pre-charge operation may be performed by applying a bank address for a bank to be pre-charged according to a pre-charge command to a memory device.
When an active command is input into the memory device, the memory device may enable a word line, and read or write data by connecting a bit line and a cell capacitor through a cell transistor. Then, when a pre-charge command is input into the memory device, the memory device turns off the cell transistor by disabling an enabled word line after a given delay time, and disconnects the bit line from the cell capacitor. At this time, time until the word line is disabled after receiving the pre-charge command is constantly set, but the time can vary with a voltage, a temperature, a process distribution, and the like.
When the time until the word line is disabled after receiving the pre-charge command becomes longer due to a voltage, a temperature, a process distribution, and the like, the memory device may perform an active operation in a state where a bit line is not properly pre-charged. On the other hand, when the time until the word line is disabled after receiving the pre-charge command becomes shorter due to a voltage, a temperature, a process distribution, and the like, time until the word line is enabled is reduced, and thereby data write time of the cell capacitor may be reduced.